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brook t ree brooktree corporation ? 9868 scranton road ? san diego, ca 92121-3707 ? 619-452-7580 1-800-2-bt-apps ? fax: 619-452-1249 ? internet: apps@brooktree.com ? l856001 rev. c BT857 bt856 ycrcb or rgb to ntsc/pal digital video encoder functional block diagram distinguishing features rgb or ycrcb inputs, selectable on a pixel-by-pixel basis ntsc/pal/pal?/pal? (argentina) composite video output s-video/rgb outputs supported ccir 601 or square pixel operation 2x oversampling 9-bit dacs master or slave video timing noninterlaced operation macrovision support (BT857 only) closed captioning encoding power-down mode scart support (rgb outputs) ? 2 c interface on-board voltage reference internal color bar generator 68-pin plcc package related products bt819 bt851 bt856evm applications digital set top box direct broadcast satellite (dbs) digital video disk (dvd) digital vcr videocd the bt856/7 is designed specically for video systems requiring the generation of 525-line (ntsc/pal?) or 625-line (pal?, d, g, h, i, n, n-argentina) compos- ite or y/c (s-video) signals. the bt856 and BT857 are functionally identical, with the exception that BT857 can output the macrovision anticopy algorithm. horizontal sync (hsync*) and vertical sync (vsync*) may be con?ured as inputs (slave mode) or outputs (master mode). blank* is an input and may be externally controlled. 24-bit linear or gamma-corrected rgb data or 4:2:2 ycrcb data may be input. the rise and fall times of sync, the burst envelope, and closed caption data are inter- nally controlled. analog luminance (y) and chrominance (c) information is available on the y and c outputs for interfacing to s-video equipment. the composite analog video signal is output simultaneously onto two analog outputs. this allows one output to provide baseband composite video and another output to drive an rf modulator. analog rgb is available to support the european scart/peritv interface. internal reset* c/r y/cvbs cvbs/g comp 1.3 mhz lpf vref_in fsadjust dac dac dac cvbs/b dac 9 gamma correct color space vref_out latch r[0:7] g[0:7] b[0:7] hsync* vsync* blank* clkx2 clkx1 pa l interlace square gamma* ycmode rgbout iic clock iic data convert mod. and mixer 2 x upscaling 9 9 9 field slave sleep vref
copyright ?1994, 1995 brooktree corporation. all rights reserved. print date: 07/21/95 brooktree reserves the right to make changes to its products or speci?ations to improve performance, reliability, or manufacturability. information furnished by brooktree corporation is believed to be accurate and reliable. however, no responsibility is assumed by brooktree corporation for its use; nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by its implication or otherwise under any patent or patent rights of brooktree corporation. brooktree products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a brooktree product can reasonably be expected to result in personal injury or death. brooktree customers using or selling brooktree products for use in such applications do so at their own risk and agree to fully indemnify brooktree for any damages resulting from such improper use or sale. brooktree is a registered trademark of brooktree corporation. product names or services listed in this publication are for identi?ation purposes only, and may be trademarks or registered trademarks of their respective companies. speci?ations are subject to change without notice. printed in the united states of america model number package ambient temperature range bt856kpj 68-pin plastic j-lead 0? to +70?c BT857kpj 68-pin plastic j-lead 0? to +70?c ordering information
brook t ree iii t able of c ontents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pixel input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 24-bit rgb input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 16-bit ycrcb input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-bit ycrcb input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 cbflag timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 field output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pixel blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 burst blanking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 digital processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 chrominance disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 subcarrier phasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 vertical blanking intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 noninterlaced operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pixel input ranges and colorspace conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 rgb inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 yc inputs (4:2:2 ycrcb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 dac coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
brook t ree iv t able of c ontents bt856/7 closed captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 anticopy process (BT857 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 internal color bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 scart/peritv support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 software programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 luminance or cvbs (y/cvbs) analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 chrominance or red (c/r) analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 composite video or blue (cvbs/b) output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 composite video (cvbs/g) analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 internal register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 pc board considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 power and ground planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 device decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 comp decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 vref _in decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 digital signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 analog signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 esd and latchup considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 sync and burst timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 clock and subcarrier stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 filtering rf modulator connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 i 2 c programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 data transfer on the i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 parametric information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 dc electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
brook t ree v l ist of f igures bt856/7 list of figures figure 1. bt856/7 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. interlaced 525-line (ntsc, pal-m) video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4a. interlaced 625-line (pal?, d, g, h, i, n, n-argentina) video timing . . . . . . . . . . . . . . . 8 figure 4b. interlaced 625-line (pal?, d, g, h, i, n, n-argentina) video timing . . . . . . . . . . . . . . . 9 figure 5. noninterlaced 262-line (ntsc, pal-m) video timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. noninterlaced 312-line (pal?, d, g, h, i, n, n-argentina) video timing . . . . . . . . . . . 10 figure 7. three-stage chroma filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. luminance upsampling filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. 525-line (ntsc/pal?) y (luminance) video output waveform . . . . . . . . . . . . . . . . . 22 figure 10. 625-line (pal?, d, g, h, i, n, n-argentina) y (luminance) video output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. 525-line (ntsc/pal?) c (chrominance) video output waveform . . . . . . . . . . . . . . . 24 figure 12. 625-line (pal?, d, g, h, i, n, n-argentina) c (chrominance) video output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 13. composite 525-line (ntsc/pal?) video output waveform . . . . . . . . . . . . . . . . . . . . 26 figure 14. composite 625-line (pal?, d, g, h, i, n, n-argentina) video output waveform . . . . 27 figure 15. typical connection diagram and parts list (external voltage reference) . . . . . . . . . . . 34 figure 16. typical connection diagram and parts list (internal voltage reference) . . . . . . . . . . . . 35 figure 17. iic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 18. 24-bit rgb and 16-bit ycrcb video input and output timing . . . . . . . . . . . . . . . . . . . . . 46 figure 19. 8-bit ycrcb video input and output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 20. 68-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
brook t ree vi l ist of t ables bt856/7 list of tables table 1. dac output cross-reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 2. 525-line (ntsc/pal?) y (luminance) video output truth table . . . . . . . . . . . . . . . . . . 22 table 3. 625-line (pal?, d, g, h, i, n, n-argentina) y (luminance) video output truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 4. 525-line (ntsc/pal?) c (chrominance) video output truth table. . . . . . . . . . . . . . . . 24 table 5. 625-line (pal?, d, g, h, i, n, n-argentina) c (chrominance) video output truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. composite 525-line (ntsc/pal?) video output truth table . . . . . . . . . . . . . . . . . . . . . 26 table 7. composite 625-line (pal?, d, g, h, i, n, n-argentina) video output truth table . . . . . 27 table 8. rgb output table (rgbout = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9. field resolutions and clock rates for various modes of operation . . . . . . . . . . . . . . . . . 38 table 10. horizontal counter values for various video timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 11. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 13. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 14. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
brook t ree 1 c ircuit d escription pin descriptions pin name i/o pin # description cvbs/b o 2 composite video with blanking and sync, or blue. cvbs/g o 4 composite video with blanking and sync, or green. c/r o 6 modulated chrominance, or red. y/cvbs o 8 luminance (with blanking, sync, and, optionally, macrovision pulses, and/or closed-captioning encoding), or composite video. rgbout i 10 analog rgb control input (ttl compatible). a logical one con?ures the device to output analog rgb (rgbout mode). a logical zero con- ?ures the device to generate s-video along with a second composite video output. this pin may be connected directly to vaa or gnd. field o 11 field control output (ttl compatible). field transitions after the rising edge of clock, two clock cycles following falling hsync*. it is a logi- cal zero during odd ?lds and is a logical one during even ?lds. test i 12, 27 these pins are reserved for testing and must be connected to a logical zero, such as gnd, for normal operation. gamma* i 25 rgb gamma control input (ttl compatible). in rgb mode, a logical zero enables the gamma correction circuitry. for rgb mode, a logical one provides a linear response. in 8-bit yc mode, this pin is used to select between inputs on b0?7 (logical one) or g0?7 (logical zero) pixel ports. in rgbout mode, if bit d4 of register 0xdc is low, this pin can be used to enable upsampling (logical zero) or disable upsampling (logical one). in rgbout mode, the gamma* pin will also select an oversampling ?ter (on the g0?7 port for 8-bit ycmode) when low, unless overridden by the combination of bits d2 at subaddress 0xda and d4 at subaddress 0xdc. this override will enable/disable oversam- pling for any input to rgb outputs. this pin may be connected directly to vaa or gnd. yc mode i 26 rgb or ycrcb select input (ttl compatible). a logical one con?ures the pixel inputs for ycrcb operation (yc mode). a logical zero con?- ures the pixel inputs for rgb operation (rgb mode), and can be switched on each clock cycle. this pin may be connected directly to vaa or gnd.
brook t ree 2 c ircuit d escription pin descriptions bt856/7 sleep i 44 powerdown control input (ttl compatible). a logical one con?ures the device for power-down mode. a logical zero con?ures the device for normal operation. this pin may be connected directly to vaa or gnd. iic data i/o 45 serial interface data input/output (ttl compatible). data is written to and read from the device via this serial bus. iic clock i 46 serial interface clock input (ttl compatible). the maximum clock rate is 100 khz. slave i 47 slave/master mode select input (ttl compatible). a logical one con?- ures the device for slave video timing operation. a logical zero con?- ures the device for master video timing operation. this pin may be connected directly to vaa or gnd. this pin is ignored if bit d4 of subad- dress register 0xdc is a logical one. clkx2 i 48 2x pixel clock input (ttl compatible). clkx1 i 49 pixel clock input (ttl compatible). inverted and sampled by clkx2 to derive clock. reset* i 52 reset control input (ttl compatible). a logical zero for one clock cycle resets and disables video timing (horizontal, vertical, subcarrier counters to the start of vsync of ?st ?ld). a logical zero for two clock cycles also resets internal registers to 00. reset* must be a logical one for normal operation, commencing at the start of vsync. blank* i 53 composite blanking control input (ttl compatible). blank* is regis- tered on the rising edge of clock. the r0?7, g0?7, and b0?7 inputs are ignored while blank* is a logical zero. vsync* i/o 54 vertical sync input/output (ttl compatible). as an output (master mode operation), vsync* is output following the rising edge of clock. as an input (slave mode operation), vsync* is registered on the rising edge of clock. hsync* i/o 55 horizontal sync input/output (ttl compatible). as an output (master mode operation), hsync* is output following the rising edge of clock. as an input (slave mode operation), hsync* is registered on the rising edge of clock. square i 58 square pixel/ccir 601 resolution select input (ttl compatible). a logi- cal one con?ures the device for square pixel operation. a logical zero con?ures the devices for ccir 601 resolution operation. this pin should be connected directly to gnd if using i 2 c. this pin is ignored if bit d4 of subaddress register 0xdc is a logical one, or if pal m or n-argentina is selected via bits d0, d1 of register 0xda. interlace i 59 interlaced/noninterlaced mode select input (ttl compatible). a logical one con?ures the device for interlaced operation. a logical zero con?- ures the device for noninterlaced operation. this pin should be con- nected directly to gnd if using i 2 c. this pin is ignored if bit d4 of subaddress register 0xdc is a logical one. pin name i/o pin # description
brook t ree 3 c ircuit d escription pin descriptions bt856/7 pal i 60 ntsc/pal mode select input (ttl compatible). a logical one con?- ures the device for pal (b, d, g, h, i, n) operation. a logical zero con- ?ures the device for ntsc operation. this pin should be connected directly to gnd if using i 2 c. for non-i 2 c use, a 10 k w pullup resistor (to vaa) must be used to program the bt856/7 for pal operation. since this pin is also used as an analog test pin, it cannot be connected directly to vaa or vdd. this pin is ignored if bit d4 of subaddress register 0xdc is a logical one. to enable pal? or pal? (argentina), bits d1 and d0 of register 0xda and d5 of register 0xdc (for pal-m setup) must be set. fs adjust 62 full-scale adjust control pin. a resistor (rset) connected between this pin and gnd controls the full-scale output current on the analog out- puts. for standard operation, use the nominal rset values shown under recommended operating conditions. the relationship between rset and the full-scale output current on the dac outputs is: rset ( w ) = 2,055 * vref_in (v) / iout fs (ma) vref_in i 63 voltage reference input. vref_in may be connected directly to vref_out. an external voltage reference can supply this input with a 1.235 v (typical) reference. a 0.1 m f ceramic capacitor must be used to decouple this input to gnd, as shown in figures 15 and 16 in the pc board layout section. the decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. vref_out o 64 voltage reference output. this pin should only be used to drive the vref_in pin. see figure 16. comp 67 compensation pin. a 0.1 m f ceramic capacitor must be used to bypass this pin to vaa. the capacitor must be as close to the device as possi- ble to keep lead lengths to an absolute minimum. r0?7, g0?7, b0?7 i 13,14, 17?0, 23,24 36?3, 28?5 rgb or ycrcb (g7:b0) pixel inputs (ttl compatible). a higher index corresponds to a greater signi?ance. vaa 16,22, 51,57, 61,65, 66 analog power. all vaa pins must be connected together on the same pcb plane to prevent latchup. gnd 15,21,50,56 68 1,3,5,7,9 analog ground. all gnd pins must be connected together on the same pcb plane to prevent latchup. pin name i/o pin # description
brook t ree 4 c ircuit d escription pin descriptions bt856/7 figure 1. bt856/7 pinout diagram vaa fs adjust vref_in vref_out vaa vaa comp gnd gnd cvbs/b gnd cvbs/g gnd c/r gnd y/cvbs gnd pa l interlace square vaa gnd hsync* vsync* blank* reset* vaa gnd clkx1 clkx2 slave iic clock iic data sleep 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 g7 g6 g5 g4 g3 g2 g1 g0 b7 b6 b5 b4 b3 b2 b1 b0 test 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 rgbout field test r0 r1 gnd vaa r2 r3 r4 r5 gnd vaa r6 r7 gamma* ycmode
brook t ree 5 c ircuit d escription pin descriptions bt856/7 a detailed block diagram of the bt856/7 is shown in figure 2. figure 2. detailed block diagram internal voltage reference 2x b[0:7] rgbout rgb gamma correction vref_in fs adjust cvbs/g y/cvbs c/r dac dac dac upsample + g 8 g[0:7] 8 r[0:7] 8 clkx1 ntsc blanking pedestal slave square pa l interlace gamma* y blank* video timing control reset* sync rise/fall expander + + 1.3 mhz lpf and 2x upsample u/v modulator 9 clkx2 iic clock sleep iic data color space convert ycmode and mixer 2x upsample 9 9 b 9 r 9 9 (averaging) g b r 9 cvbs/g dac 9 9 vref_out 9 9 9 9 9 9 field hsync* vsync* comp blank* 9
brook t ree 6 c ircuit d escription clock timing bt856/7 clock timing both clkx1 and clkx2 must be supplied to bt856/7. the internal clock is derived by registering inverted clkx1 with the rising edge of clkx2. synchro- nous inputs and outputs are registered by the rising edge of clock, except in 8-bit ycrcb input mode where cb/cr are registered on the falling edge of clock. the timing parameters speci?d under ac characteristics in the para- metric information section are de?ed with respect to clkx2. inputs must be val- id for the minimum speci?d setup time prior to the rising edge of clkx2 while clkx1 is low (except in 8-bit ycrcb mode where cb/cr are registered while clkx1 is high). pixel input timing 24-bit rgb input mode r0?7, g0?7, b0?7 are registered on the rising edge of clock. this mode is enabled by setting the ycmode pin low. 16-bit ycrcb input mode this mode is available by setting the ycmode pin high. y0?7 data is input via the g0?7 inputs; multiplexed cb0?b7 and cr0?r7 data is input via the b0?7 inputs. g0?7 and b0?7 are registered on the rising edge of clock. r0?7 and gamma* pins are ignored. 8-bit ycrcb input mode the 8-bit ycrcb multiplexed input mode is selected by setting the ycmode pin high and by setting register bit d7 of register 0xdc to a 1. multiplexed y, cb, and cr data is input through the g0?7 inputs or through the b0?7 inputs. the gamma* pin is used to select between the two different 8-bit ports: if gamma* is high, ycrcb is input through b0?7; if gamma* is low, ycrcb is input through g0?7. by default, the input sequence for active video pixels must be cb0, y0, cr0, y1, cb2, y2, cr2, y3, etc. in accordance with ccir656. y and cb/cr are registered during a single clock period. cb or cr is regis- tered ?st, on the falling edge of clock; y is registered next, on the rising edge of clock. cbflag timing by default, cb data is input during odd (base1) values of the horizontal counter while cr data is registered during even counts. cb data may be input during even values of the horizontal counter by writing a 1 to register bit d6 of register 0xdc. the falling edge of hsync* corresponds to a horizontal count of one (default af- ter reset* cycle) unless the bt856/7 is con?ured in master mode with program- mable hsync* output timing.
brook t ree 7 c ircuit d escription video timing bt856/7 video timing the width of the analog horizontal sync pulses and the start and end of color burst is automatically calculated and inserted for each mode according to ccir624-4. color burst is disabled on appropriate scan lines. serration and equalization pulses are gen- erated on appropriate scan lines. in addition, rise and fall times of sync, closed-cap- tion data transitions, and the burst envelope are internally controlled. figures 3? show the timing characteristics for various bt856/7 modes of operation. figure 3. interlaced 525-line (ntsc, pal-m) video timing note: smpte line numbering convention rather than ccir624 is used. 22 7 6 5 4 3 burst phase 2 1 525 524 523 analog field 1 start of vsync analog field 2 272 271 270 269 268 267 263 262 261 266 265 264 285 analog field 3 burst phase analog field 4 burst begins with positive half-cycle burst phase = reference phase = 180? relative to b? burst begins with negative half-cycle burst phase = reference phase = 180? relative to b? 89 10 22 7 6 5 4 3 2 1 525 524 523 89 10 272 271 270 269 268 267 263 262 261 266 265 264 285
brook t ree 8 c ircuit d escription video timing bt856/7 figure 4a. interlaced 625-line (pal?, d, g, h, i, n, n-argentina) video timing 24 7 6 5 4 3 ?u phase 2 1 622 621 620 analog field 1 start of vsync 625 624 623 23 analog field 2 337 320 318 317 316 315 314 309 308 312 311 336 319 337 320 317 316 315 314 308 313 312 311 336 319 310 313 309 318 310 24 7 6 5 4 3 2 1 622 621 620 625 624 623 23 field one field two field three field four burst blanking intervals burst phase = reference phase = 135? relative to u pal switch = 0, +v component burst phase = reference phase + 90? = 225? relative to u pal switch = 1, ? component analog field 3 analog field 4
brook t ree 9 c ircuit d escription video timing bt856/7 figure 4b. interlaced 625-line (pal?, d, g, h, i, n, n-argentina) video timing 24 7 6 5 4 3 ?u phase 2 1 622 621 620 analog field 5 start of vsync 625 624 623 23 337 320 318 317 316 315 314 309 308 312 311 336 319 337 320 317 316 315 314 308 313 312 311 336 319 310 313 309 318 310 24 7 6 5 4 3 2 1 622 621 620 625 624 623 23 field five field six field seven field eight burst blanking intervals burst phase = reference phase = 135? relative to u pal switch = 0, +v component burst phase = reference phase + 90? = 225? relative to u pal switch = 1, ? component analog field 6 analog field 7 analog field 8
brook t ree 10 c ircuit d escription video timing bt856/7 figure 5. noninterlaced 262-line (ntsc, pal-m) video timing 18 7 6 5 1 262 261 260 259 258 start of vsync burst begins with positive half-cycle burst phase = reference phase = 180? relative to b? 234 reset* 18 7 6 5 1 262 261 260 259 258 234 burst begins with negative half-cycle burst phase = reference phase = 180? relative to b? figure 6. noninterlaced 312-line (pal?, d, g, h, i, n, n-argentina) video timing 23 7 6 5 1 312 311 310 309 308 start of vsync 23 4 reset* 24 23 7 6 5 1 312 311 310 309 308 23 4 24 burst phase = reference phase = 135? relative to u pal switch = 0, +v component burst phase = reference phase + 90? = 225? relative to u pal switch = 1, ? component
brook t ree 11 c ircuit d escription video timing bt856/7 reset if the reset* pin is held low during a single rising edge of the internally gener- ated clock signal, the subcarrier phase is set to zero, and the horizontal and ver- tical counters are set to the beginning of vsync of field1. counting resumes the ?st rising edge of clock after rising reset*. in addition to the timing reset, if the reset* pin is held low for two consecu- tive low-to-high transitions of clock, a software reset occurs, setting all of the software programmable registers bits to zero. master mode horizontal sync (hsync*) and vertical sync (vsync*) are generated from in- ternal timing and from optional software bits. hsync* and vsync* are output following the rising edge of clock. the horizontal counter is incremented on the rising edge of clock. after reaching the appropriate value (determined by the mode of operation), it is reset to one, indicating the start of a new line. the vertical counter is incremented at the start of each new line. after reaching the appropriate value (determined by the mode of operation), it is reset to one, in- dicating the start of a new ?ld (interlaced operation) or frame (noninterlaced op- eration). the hsync* output may be con?ured to have standard video timing (4.7 m s wide, asserted at start of a line default after reset cycle) or it may be pro- grammed to specify the start of hsync* (10-bit value) and the end of hsync* (10-bit value). vsync* is asserted for 3 or 2.5 scan lines for 262/525 line and 312/625 line, respectively. when hsync* is con?ured for standard video tim- ing, coincident falling edges of hsync* and vsync* indicate the beginning of an odd ?ld. slave mode horizontal sync (hsync*) and vertical sync (vsync*) are inputs that are regis- tered on the rising edge of clock. the horizontal counter is incremented on the rising edge of clock. a falling edge of hsync* resets it to one, indicating the start of a new line. the vertical counter is incremented on the falling edge of hsync*. a falling edge of vsync* resets it to one, indicating the start of a new ?ld (interlaced op- eration) or frame (noninterlaced operation). a falling edge of vsync* that occurs within 1/4 of a scan line from the fall- ing edge of hsync* indicates the beginning of an odd ?ld. a falling edge of vsync* that occurs within 1/4 scan line from the center of the line indicates the beginning of an even ?ld. referring to figures 3?, start of vsync occurs on the falling hsync* at the beginning of the next expected odd ?ld and halfway be- tween expected falling hsync* edges at the beginning of the next expected even ?ld. the operating mode is automatically determined when con?ured as a slave. the pal, interlace, and square pins are ignored. the mode override reg- isters can still be used to force a particular mode. 525-line operation is assumed; 625-line operation is detected by the number of lines in a ?ld. interlaced opera- tion is detected by observing the sequence of odd or even ?lds; if the ?ld timing (odd follows odd, even follows even) is repeated, then noninterlaced mode is as-
brook t ree 12 c ircuit d escription video timing bt856/7 sumed. the frequency of operation (square pixels or ccir) for both pal and ntsc is detected by counting the number of clocks per line. the sampling note is assumed to be 13.5 mhz unless the exact horizontal count for square pixels, 1 count, is detected in between two successive falling edges of hsync*. note: square pixel 625-line operation with this sequence requires one frame to stabilize. field output the field output indicates whether an odd ?ld (logical zero) or even ?ld (log- ical one) is being generated. field changes are detected by the falling edge of vsync*. field is output following the rising edge of clock. unless special hsync* timing is programmed, field output transitions low, two clock pe- riods following the falling edge of hsync* at the beginning of an odd ?ld. this corresponds directly to the bottom/top* convention of some mpeg decoders. pixel blanking blank* is registered on the rising edge of clock. for rgbout mode, rgb video is blanked for each clock period in which the blank* input is low. for vid- eo outputs, blank* is pipelined to match the luminance and chrominance paths and is applied to the digital video before analog conversion. the automatic hori- zontal blanking sequence described in table 10 (in the pc board considerations section) take precedence over the blank* input. burst blanking for interlaced ntsc/pal?, color burst information is automatically disabled on scan lines 1? and 264?69, inclusive. (smpte line numbering convention.) for interlaced pal?, d, g, h, i, n, n-argentina, color burst information is automatically disabled on scan lines 1?, 310?18, and 623?25, inclusive, for ?lds 1, 2, 5, and 6. during ?lds 3, 4, 7, and 8, color burst information is disabled on scan lines 1?, 311?19, and 622?25, inclusive. for noninterlaced ntsc/pal?, color burst information is automatically dis- abled on scan lines 1? and 261?62, inclusive. for noninterlaced pal?, d, g, h, i, n, n-argentina, color burst information is automatically disabled on scan lines 1? and 310?12, inclusive. see figures 3?. digital processing once the input data is converted into internal yuv format, the uv components are low-pass ?tered with a ?ter response shown in figure 7 (linearly scalable by clock frequency). the y and ?tered uv components are upsampled to clkx2 frequency by a digital ?ter whose response is shown in figure 8. chrominance disable the chrominance subcarrier may be turned off by setting bit d5 of register subad- dress 0xde to a logical one. this kills burst as well, providing luminance only sig- nals on the cvbs outputs and a static blank level on the c/r output (rgbout=0).
brook t ree 13 c ircuit d escription video timing bt856/7 figure 7. three-stage chroma filter 5 0 ?5 ?15 ?20 ?25 ?30 ?35 ?40 ?10 frequency mhz attenuation db 0 0.5 1 1.5 2 clock =13.5 mhz figure 8. luminance upsampling filter response 5 0 ?5 ?15 ?20 ?25 ?30 ?35 ?40 ?10 frequency mhz attenuation db 0612 24 810 clock =13.5 mhz
brook t ree 14 c ircuit d escription video timing bt856/7 subcarrier phasing in order to maintain correct sc-h phasings, subcarrier phase is set to zero on the falling edge of hsync* associated with vsync* every four (ntsc) or eight (pal) ?lds, unless bit d3 of register 0xde is set to a logical one. in slave mode, falling hsync* may lag falling vsync* by 1/4 scan line but cannot precede falling vsync* by more than 14 clock periods for correct sc-h reset. setting d3 to one may be useful in situations where the ratio of clocks/hsync* edges in a color frame is non-integer, which could produce a signi?ant phase impulse by resetting to zero. for a perfect clock input, the burst frequency is 4.43361875 mhz for pal?, d, g, h, i, n, 3.57561149 for pal?, 3.58205625 for pal? (argentina), 3.579545 mhz for ntsc interlaced, and 3.579515 mhz for ntsc noninterlaced. vertical blanking intervals for interlaced ntsc/pal?, scan lines 1? and 263?72, inclusive, are always blanked regardless of the blank* input. there is no setup on scan lines 10?1 and 273?84, inclusive, allowing the generation of video test signals, timecode, and other information by controlling the pixel inputs appropriately (except for lines controlled by closed caption or macrovision generation). for interlaced pal?, d, g, h, i, n, n-argentina, scan lines 1?, 311?18, and 624?25, inclusive, during ?lds 1, 2, 5, and 6, are always blanked regardless of the blank* input. during ?lds 3, 4, 7, and 8, scan lines 1?, 311?19, and 624?25, inclusive, are always blanked regardless of the blank* input. the re- maining scan lines during the vertical blanking interval may be used for the gen- eration of video test signals, timecode, and other information by controlling the pixel inputs appropriately. alternately, all displayed lines in the vertical blanking interval (10?1 and 273?84 for interlaced ntsc/pal?; 7?3 and 320?35 for interlaced pal?, d, g, h, i, n, n-argentina) may be forced blanked by setting bit d2 to a logical one in register 0xde (except for caption lines controlled by bit d6 and d7 or mac- rovision process). for noninterlaced ntsc/pal?, scan lines 1?, inclusive, are always blanked regardless of the blank* input. for noninterlaced pal?, d, g, h, i, n, n-ar- gentina, scan lines 1? and 311?12, inclusive, are always blanked regardless of the blank* input. bit d2 at register 0xde will blank lines 10?1 for ntsc/pal? or lines 7?3 for pal?, d, g, h, i, n, n-argentina, except for closed captions on lines 21 (22) and 284 (335), controlled by bits d6 and d7, or for macrovision process.
brook t ree 15 c ircuit d escription video timing bt856/7 noninterlaced operation the device can be operated in noninterlaced mode by setting the interlace pin to a logical zero. when in noninterlaced master mode, the bt856/7 always displays the odd-?ld, meaning that the falling edges of hsync* and vsync* will be output coincidentally. field will change state with each vsync* edge. addi- tionally, a 30 hz offset will be subtracted from the color subcarrier frequency while in ntsc/pal? mode so that the color subcarrier phase will be inverted from ?ld to ?ld. subcarrier phase is reset to zero upon rising reset* and every 4 ?lds of ntsc/pal? or 8 ?lds of pal?, d, g, h, i, n, n-argentina, unless bit d3 in register 0xde is a logical one. transition from interlaced to noninterlaced in master mode, occurs during odd ?lds to prevent synchronization disturbance. in slave mode, transition occurs af- ter a subsequent falling edge of vsync*. note: consumer vcrs can record noninterlaced video with minor noise arti- facts, but special effects (e.g., scan > 2x) may not function properly. power-down mode in power-down mode (sleep pin set to 1), register states are preserved, but other chip functionality (including i 2 c communication) is disabled. this mode should be set when the bt856/7 may be subjected to clock and data frequencies outside its functional range.
brook t ree 16 c ircuit d escription pixel input ranges and colorspace conversion bt856/7 pixel input ranges and colorspace conversion rgb inputs with ycmode set to a logical zero (rgb mode), digital rgb data with a 0?55 range is input via the r0?7, g0?7, and b0?7 inputs. by default, the gray-scale range of 0?55 represents 7.5?00 ire for ntsc, or 300?000 mv for pal. alternatively, software bit d5 of register 0xdc can alter pixel scaling and dis- able or enable the 7.5 ire setup. when this bit is enabled, pal video can be gen- erated using ntsc/pal? blanking levels and 7.5 ire setup, and default ntsc/pal? pixel scaling is applied (0?55 represents 7.5?00 ire); or, ntsc/pal? video can be generated using pal scaling (0?55 represents 0?00 ire) without the 7.5 ire setup. ntsc mode with setup disabled has 2% less black-to-white range compared to setup enabled. if the gamma* pin is high, no prescaling is performed to compensate for gam- ma characteristics of the receiver. if gamma* is low, gamma pre-correction is applied per ccir 709. in the following equations, x represents the pixel input val- ue and g represents the corrected value. 525-line systems (ntsc, pal?): for x < 5, g = 4.5 * x for x > 4, g = 255 * (1.099 * (x/255)(1/2.2) ?0.099) 625-line systems (pal?, d, g, h, i, n, n?rgentina): for x < 5, g = 9 * x for x > 4, g = 255 * (1.099 * (x/255)(1/2.8) ?0.099) the standard ccir 624 matrix is used to convert rgb to yuv: y = +0.299r + 0.587g + 0.114b u = ?.147r ?0.289g + 0.436b v = +0.615r ?0.515g ?0.100b ntsc 33% axis rotation is performed in the subcarrier encoding. data is round- ed to the nearest 9-bit dac value. for rgbout mode (rgbout = 1 with yc mode = 0), the 8-bit rgb inputs directly feed the 9-bit dacs without any scaling or level-shifting. therefore, only half of the current drive is available in this mode. gamma precorrection is not ap- plied to rgb outputs. an averaging interpolation ?ter is available to upsample the rgb pixel stream. upsampling is enabled or disabled in either of two ways: with the gamma* pin or with software bit d2 of register 0xda. the pin-override switch (bit d4 of reg- ister 0xdc) determines which method has priority: if the override is high, then software is used; if the override is low, then the gamma* pin is used. in both cas- es (gamma* pin or bit d2 of register 0xda), a logical low enables upsampling and a logical high disables upsampling. the pipeline delay is the same regardless of whether upsampling is active or not (please see ac characteristics for pipeline delay).
brook t ree 17 c ircuit d escription pixel input ranges and colorspace conversion bt856/7 yc inputs (4:2:2 ycrcb) y has a nominal range of 16?35; cb and cr have a nominal range of 16?40, with 128 equal to zero. values of 0 and 255 are interpreted as 1 and 254, respectively. y values of 1?5 and 236?54, and crcb values of 1?5 and 241?54, are interpret- ed as valid linear values. alternatively, software bit d5 of register 0xdc can alter pixel scaling and dis- able or enable the 7.5 ire setup. when this bit is enabled, pal?, d, g, h, i, n, n-argentina video can be generated using ntsc/pal? blanking levels and 7.5 ire setup, and ntsc/pal? pixel scaling is performed (y range of 16-235 rep- resents 7.5-100 ire); or, ntsc/pal? video can be generated using pal?, d, g, h, i, n, n-argentina scaling (y range of 16-235 represents 0-100 ire) without the 7.5 ire setup. ntsc/pal? mode with setup disabled has 2% less black-to-white range than ntsc/pal? mode with setup enabled. for rgbout mode, 4:2:2 ycrcb digital component video will be used to gen- erate composite video and will be converted to the rgb colorspace to drive the rgb dacs. the y input range of 16?35 will produce a range of 0.7 v at the out- put. since yc values outside of the nominal range are allowed, the black level is raised above zero volts to allow for y values less than 16, and the output range of the dacs can exceed 0.7 v to allow for y values above 235. the conversion is lin- early scaled in the overshoot and undershoot regions. the following matrix, based on ccir 601, is used to convert ycrcb to rgb: r = y + 1.371*cr g = y ?0.699*cr ?0.337*cb b = y + 1.733*cb values are rounded to 9-bits at the dac. an averaging interpolation ?ter is available to upsample the rgb pixel stream. upsampling is enabled or disabled in either of two ways: with the gamma* pin or with software bit d2 of register 0xda. the pin-override switch (bit d4 of reg- ister 0xdc) determines which method has priority: if the override is high, then software is used; if the override is low, then the gamma* pin is used. in both cas- es (gamma* pin or bit d2 of register 0xda), a logical low enables upsampling and a logical high disables upsampling. the pipeline delay is the same regardless of whether upsampling is active or not (please see ac characteristics for pipeline delay). dac coding white is represented by a dac code of 400. for pal?, d, g, h, i, n, n-argen- tina, the standard blanking level is represented by a dac code of 120. for ntsc/pal?, with setup enabled (bit d5 of register 0xdc is ??, the standard blanking level is represented by a dac code of 114, 1 ire is equivalent to a dac code of 2.857. for ntsc/pal? with setup disabled (bit d5 of register 0xdc is ??, the standard blanking level is represented by a dac code of 112, 1 ire is equivalent to a dac code of 2.800.
brook t ree 18 c ircuit d escription closed captioning bt856/7 closed captioning the bt856/7 encodes ntsc/pal? closed captioning on scan line 21 and ntsc/pal? extended data services on scan line 284. four 8-bit registers (sub- address 0xd0?4) provide the data while bits d6 and d7 at subaddress 0xde en- able display of the data. a logical zero corresponds to the blanking level of 0 ire, while a logical one corresponds to 50 ire above the blanking level. closed captioning for pal?, d, g, h, i, n, n-argentina is similar to that for ntsc. closed caption encoding is performed for 625-line systems according to the system proposed by the national captioning institute; clock and data timing is identical to that of ntsc system, except that encoding is provided on lines 22 and 335. the bt856/7 generates the clock run-in and appropriate timing automatically. pixel inputs are ignored during cc encoding. see fcc code of federal regula- tions (cfr) 47 section 15.119 (10/91 edition or later) for programming informa- tion. eia608 describes ancillary data applications for field 2 line 21 (line 284). note: register contents are transferred immediately following the clock run-in, and must be stable for the duration of the line generated. anticopy process (BT857 only) the anticopy process contained within the BT857 is implemented according to the macrovision revision 6 speci?ation developed by macrovision in mountain view, california. all luminance, chrominance, and composite video waveforms include the macrovision anticopy process. the BT857 incorporates an anticopy process technology that is protected by u.s. patents and other intellectual property rights. the anticopy process is licensed for non-commercial, home use only. reverse engineering or disassembly is prohibited. brooktree cannot ship BT857 units to any customer until that customer has been approved by macrovision. to obtain approval for shipment of BT857 samples, a ?acrovision proprietary material license agreement?is required. contact mac- rovision at 415-691-2900 (fax: 415-691-2999) to facilitate this agreement.
brook t ree 19 c ircuit d escription internal color bars bt856/7 internal color bars the bt856/7 can be con?ured to generate 75% amplitude, 100% saturation (75/7.5/75/7.5 for ntsc/pal? with setup; 75/0/75/0 for pal) color bars, re- gardless of the gamma* pin state. if the iic data pin is held high during the rising edge of reset*, color bars are automatically enabled. otherwise, following a reset, colorbars can be enabled or disabled by writing a one or a zero into bit d4 of register 0xde. with the excep- tion of the ycmode and gamma* pins, all pins and registers can be changed and reprogrammed while generating color bars, thereby simplifying testing of var- ious modes. if the iic data pin is held low while the reset* pin goes high, color bars will not be generated following a reset condition. the iic data pin is normally high, unless performing a data transfer or acknowledge pulse. scart/peritv support the rgbout pin may be used to con?ure the bt856/7 to generate analog rgb video signals (rather than s-video) to interface to a scart/peritv connector. when rgbout = 1, red information is output on the c/r pin, blue information is output on the cvbs/b pin, and green information is output on the cvbs/g pin. composite video will be present on the y/cvbs dac, but will not be time-aligned with rgb outputs. in rgb mode, nominal rgb amplitude is 635 mvpp with a 37.5 w load, while in yc mode, rgb outputs are 700 mvpp into 37.5 ohms.
brook t ree 20 c ircuit d escription software programming bt856/7 software programming a simpli?d i 2 c (7-bit subaddress, 100 kbps) interface is provided for program- ming the registers. all registers are write-only and are set to zero following a soft- ware reset. all data transfers and addresses are written msb ?st. the lsb for all subaddresses is zero to indicate a write condition. registers can be written if the i 2 c address 0x88 is received. the device id can be read from the iic data pin if the address 0x89 is received. the device id for the BT857 is 0xe0; for the bt856, it is 0x60. figure 17 in the pc board consider- ations section illustrates i 2 c write operations. clkx2 and clkx1 must be applied and stable for iic communication. acti- vating sleep or reset* will disable iic communication. following power up, the iic data pin may be asserted until clock cycles four times.
brook t ree 21 c ircuit d escription outputs bt856/7 outputs all digital-to-analog converters are designed to drive standard video levels into an equivalent 37.5 w load. unused outputs should be connected directly to ground to minimize supply switching currents. in standard mode (rgbout = 0), two composite video and s-video (yc) outputs are available. in rgbout mode (rgbout = 1), one composite video output along with analog rgb are available (see table 1). if the sleep pin is high, the dacs are essentially turned off and only the leakage current is present. the d/a converter values for 100% saturation, 100% amplitude color bars are shown in figures 9?4. both composite video and analog rgb video (to provide support for scart/peritv) may be generated simultaneously. luminance or cvbs (y/cvbs) analog output digital luminance information drives the 9-bit d/a converter that generates the an- alog y video output (figures 9 and 10 and tables 2 and 3). this dac can also pro- vide cvbs for scart/peritv synchronization when rgbout is enabled. chrominance or red (c/r) analog output digital chrominance information drives the 9-bit d/a converter that generates the analog c video output (figures 11 and 12 and tables 4 and 5). this dac can also provide red for scart/peritv when rgbout is enabled. composite video or blue (cvbs/b) output digital composite video information drives the 9-bit d/a converter that generates the analog ntsc or pal video output (figures 13 and 14 and tables 6 and 7). this dac can also provide blue for scart/peritv when rgbout is enabled. composite video (cvbs/g) analog output digital composite video information drives the 9-bit d/a converter that generates the analog video output (table 8). this dac can also provide green for scart/peritv when rgbout is enabled. table 1. dac output cross-reference pin name pin number pin function std mode rgb out mode cvbs/b 2 cvbs b cvbs/g 4 cvbs g c/r 6 c r y/cvbs 8 y cvbs
brook t ree 22 c ircuit d escription outputs bt856/7 figure 9. 525-line (ntsc/pal?) y (luminance) video output waveform note: typical with 37.5 w load, vref_in = vref_out, nominal rset, and setup on. smpte 170 m levels are assumed. 100% saturation color bars (100/7.5/100/7.5) are shown. 26.68 1.000 ma v 0.00 0.000 9.07 0.340 7.60 0.285 white yellow cyan green magenta red blue black white level black level blank level sync level 100 ire 40 ire 7.5 ire 400 370 321 291 245 215 166 table 2. 525-line (ntsc/pal?) y (luminance) video output truth table description iout (ma) dac data sync interval blank* white 26.68 400 0 1 black 9.07 136 0 1 blank 7.60 114 0 0 sync 0 0 1 0 note: typical with 37.5 w load, vref_in = vref_out, nominal rset, and setup on. smpte 170 m levels are assumed. 100% saturation color bars (100/7.5/100/7.5) are shown.
brook t ree 23 c ircuit d escription outputs bt856/7 figure 10. 625-line (pal?, d, g, h, i, n, n-argentina) y (luminance) video output waveform note: typical with 37.5 w load, vref_in = vref_out, setup off, and nominal rset. ccir 624 levels are assumed. 100% saturation (100/0/100/0) color bars are shown. 26.68 1.000 ma v 0.00 0.000 8.00 0.300 white yellow cyan green magenta red blue black white level black/blank level sync level 400 368 316 284 236 204 152 table 3. 625-line (pal?, d, g, h, i, n, n-argentina) y (luminance) video output truth table description iout (ma) dac data sync interval blank* white 26.68 400 0 1 black 8.00 120 0 1 blank 8.00 120 0 0 sync 0 0 1 0 note: typical with 37.5 w load, vref_in = vref_out, setup off, and nominal rset. ccir 624 levels are assumed. 100% saturation (100/0/100/0) color bars are shown.
brook t ree 24 c ircuit d escription outputs bt856/7 figure 11. 525-line (ntsc/pal?) c (chrominance) video output waveform note: typical with 37.5 w load, vref_in = vref_out, nominal rset, chroma on, and setup on. smpte 170 m levels are assumed. 100% saturation color bars (100/7.5/100/7.5) are shown. white yellow cyan green magenta red blue black color burst (9 cycles) 20 ire 20 ire 28.21 1.058 ma v 5.93 0.222 20.88 0.783 17.07 0.640 13.27 0.498 blank level table 4. 525-line (ntsc/pal?) c (chrominance) video output truth table description iout (ma) dac data sync interval blank* peak chroma (high) 28.21 423 x 1 burst (high) 20.88 313 x x blank 17.07 256 x 0 burst (low) 13.27 199 x x peak chroma (low) 5.93 89 x 1 note: typical with 37.5 w load, vref_in = vref_out, nominal rset, chroma on, and setup on. smpte 170 m levels are assumed. 100% saturation color bars (100/7.5/100/7.5) are shown.
brook t ree 25 c ircuit d escription outputs bt856/7 figure 12. 625-line (pal?, d, g, h, i, n, n-argentina) c (chrominance) video output waveform note: typical with 37.5 w load, vref_in = vref_out, nominal rset, chroma on, and setup off. ccir 624 lev- els are assumed. 100% saturation (100/0/100/0) color bars are shown. white yellow cyan green magenta red blue black color burst (10 cycles) 28.88 1.083 ma v 5.27 0.198 21.08 0.791 17.07 0.640 13.07 0.490 blank level table 5. 625-line (pal?, d, g, h, i, n, n-argentina) c (chrominance) video output truth table description iout (ma) dac data sync interval blank* peak chroma (high) 28.88 433 x 1 burst (high) 21.08 316 x x blank 17.07 256 x 0 burst (low) 13.07 196 x x peak chroma (low) 5.27 79 x 1 note: typical with 37.5 w load, vref_in = vref_out, nominal rset. chroma on, and setup off. ccir 624 levels are assumed. 100% saturation (100/0/100/0) color bars are shown.
brook t ree 26 c ircuit d escription outputs bt856/7 figure 13. composite 525-line (ntsc/pal?) video output waveform note: typical with 37.5 w load, vref_in = vref_out, nominal rset, clipping off, chroma on and setup on. smpte 170 m levels are assumed. 100% saturation color bars (100/7.5/100/7.5) are shown. 32.55 1.221 ma v 0.00 0.000 9.07 0.340 white yellow cyan green magenta red blue black white level black level blank level sync level (9 cycles) color burst 26.68 1.000 34 ire 100 ire 20 ire 7.5 ire 20 ire 40 ire 3.80 0.143 7.60 0.285 11.41 0.423 400 370 321 291 245 215 166 table 6. composite 525-line (ntsc/pal?) video output truth table description iout (ma) dac data sync interval blank* peak chroma (high) 32.55 488 0 1 white 26.68 400 0 1 burst (high) 11.41 171 0 x black 9.07 136 0 1 blank 7.60 114 0 0 burst (low) 3.80 57 0 x peak chroma (low) 3.20 48 0 1 sync 0 0 1 0 note: typical with 37.5 w load, vref_in = vref_out, nominal rset, clipping off, chroma on and setup on. smpte 170 m levels are assumed. 100% saturation color bars (100/7.5/100/7.5) are shown.
brook t ree 27 c ircuit d escription outputs bt856/7 figure 14. composite 625-line (pal?, d, g, h, i, n, n-argentina) video output waveform note: typical with 37.5 w load, vref_in = vref_out, nominal rset, setup and clipping off. ccir 624 levels are assumed. 100% amplitude, 100% saturation (100/0/100/0) color bars are shown. 32.88 1.233 ma v 0.00 0.000 26.68 1.000 1.80 0.068 4.00 0.150 8.00 0.300 white yellow cyan green magenta red blue black white level black/blank sync level (10 cycles) color burst level 12.01 0.450 400 368 316 284 236 204 152 table 7. composite 625-line (pal?, d, g, h, i, n, n-argentina) video output truth table description iout (ma) dac data sync interval blank* peak chroma (high) 32.88 493 0 1 white 26.68 400 0 1 burst (high) 12.01 180 0 x black 8.00 120 0 1 blank 8.00 120 0 0 burst (low) 4.00 60 0 x peak chroma (low) 1.80 27 0 1 sync 0 0 1 0 note: typical with 37.5 w load, vref_in = vref_out, nominal rset, setup and clipping off. ccir 624 levels are assumed. 100% amplitude, 100% saturation (100/0/100/0) color bars are shown.
brook t ree 28 c ircuit d escription outputs bt856/7 table 8. rgb output table (rgbout = 1) description iout (ma) dac data blank* yc mode white 17.04 255 1 0 black 0 0 1 0 blank 0 0 0 white (0xeb) 20.07 301 1 1 black (0x10) 1.40 21 1 1 blank 1.40 21 0 1 note: iout typical with 37.5 w load, vref_in = vref_out, nominal rset.
brook t ree 29 r egisters internal register all registers are write-only and set to zero following a reset condition. 7-bit values must be followed by a zero to form the 8-bit address. i 2 c address = 0x88 function subaddress description 7-bit 8-bit reserved 0x60?x66, 0x70?x7f 0xc0?xcd, 0xe0?xff reserved. must be zero for normal operation. ccda 0x67 0xce first byte of closed-caption data for line 284/335. ccdb 0x68 0xd0 second byte of closed-caption data for line 284/335. ccdc 0x69 0xd2 first byte of closed-caption data for line 21/22. ccdd 0x6a 0xd4 second byte of closed-caption data for line 21/22. hsync begin time 0x6b 0xd6 this register (non-zero when d7 of registers 0xda logical one) value speci?s the horizontal count (8 least signi?ant bits) when hsync* should be asserted. this register is ignored if in slave mode or if bit 7 in register 0xda is zero. the two most sig- ni?ant bits are in register 0xda. hsync end time 0x6c 0xd8 this register (non-zero when d7 of register 0xda logical one) value speci?s the horizontal count (8 least signi?ant bits) when hsync* should be deasserted. this register is ignored if in slave mode or if bit 7 in register 0xda is zero. the two most signi?ant bits are in register 0xda. a value equal to the begin value is indeterminate.
brook t ree 30 r egisters internal register bt856/7 hsync timing 0x6d 0xda bit d7 (ignored in slave mode): 0 = standard hsync timing 1 = programmable hsync timing bits d6, d5 (ignored if d7 = 0): two most significant bits for the hsync begin value. bits d4, d3 (ignored if d7 = 0): two most significant bits for the hsync end value. bit d2 (active only if bit d4 of register 0xdc = 1): 0 = enable upsampling of rgb outputs 1 = disable upsampling of rgb outputs bits d1 and d0: 3 = pal? 2 = reserved 1 = pal? (argentina) 0 = pal?, d, g, h, i, n modes and control 0x6e 0xdc bit d7 (only used when ycmode pin is high): 0 = 16-bit ycrcb 1 = 8-bit ycrcb bit d6 (ignored if rgb input format): 0 = cb0 occurs on odd horizontal count 1 = cb0 occurs on even horizontal count bit d5 (affects black level and pixel scaling): 0 = add 7.5 ire setup for active ntsc/pal? lines; do not add setup for active pal lines 1 = disable 7.5 ire setup for active ntsc/pal? lines; add equivalent 7.5 ire setup for active pal lines bit d4: 0 = use mode pins 1 = override mode pins bit d3 (active only if d4 = 1): 0 = master mode 1 = slave mode bit d2 (active only if d4 = 1): 0 = ntsc operation 1 = pal operation bit d1 (active only if d4 = 1): 0 = noninterlaced operation 1 = interlaced operation bit d0 (active only if d4 = 1): 0 = ccir 601 resolution 1 = square pixel resolution function subaddress description 7-bit 8-bit
brook t ree 31 r egisters internal register bt856/7 caption mode and control 0x6f 0xde bit d7 (line 335 for 625-line systems): 0 = disable line 284 extended data services 1 = enable line 284 extended data services bit d6 (line 22 for 625-line systems): 0 = disable line 21 closed captioning 1 = enable line 21 closed captioning bit d5: 0 = normal operation 1 = blank chroma portion of video output bit d4: 0 = normal operation 1 = enable color bars bit d3 (ignored in master mode): 0 = color subcarrier reset every 4 (ntsc) or 8 (pal) fields 1 = color subcarrier not locked to field timing bit d2: 0 = normal operation 1 = blank all lines in vertical blanking interval bit d1 (dac level for clipping composite video, ignored if d0=0): 0 = values less than 31 are made 31 1 = values less than 63 are made 63 bit d0: 0 = disable dac output clipping 1 = enable dac output clipping function subaddress description 7-bit 8-bit
brook t ree 33 pc b oard c onsiderations for optimum performance of the bt856/7, proper cmos layout techniques should be studied in the bt451/457/458 evaluation module operation and measurements, application note (an-16), before pc board layout is begun. the layout should be optimized for lowest noise on the power and ground planes by providing good decoupling. the trace length between groups of vaa and gnd pins should be as short as possible to minimize inductive ringing. a well-designed power distribution network is critical to eliminating digital switching noise. the ground plane must provide a low-impedance return path for the digital circuits. a pc board with a minimum of four layers is recommended, with layers 1 (top) and 4 (bottom) for signals and layers 2 and 3 for ground and power, respectively. component placement components should be placed as close as possible to the associated pin. whenever possible, components should be placed so traces can be connected point to point. the optimum layout enables the bt856/7 to be located as close as possible to the power supply connector and the video output connector. power and ground planes for optimum performance, a common digital and analog ground plane is recommended. separate digital and analog power planes are recommended. the digital power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all bt856/7 power pins, vref_in circuitry, and comp decoupling. there should be at least a 1/8-inch gap between the digital power plane and the analog power plane. the analog power plane should be connected to the digital power plane (vcc) at a single point through a ferrite bead, as illustrated in figures 15 and 16. this bead should be located within 3 inches of the bt856/7. the bead provides resis- tance to switching currents, acting as a resistance at high frequencies. a low-resis- tance bead should be used, such as ferroxcube 5659065-3b, fair-rite 2723021447, or tdk bf45-4001.
brook t ree 34 pc b oard c onsiderations power and ground planes bt856/7 figure 15. typical connection diagram and parts list (external voltage reference) notes: 1. values for 700 mv scart /peritv may be 20% higher when using rgb inputs. 2. some modulators may require ac coupling capacitors (10 m f). vaa comp vref_out vref_in gnd c7 c8 c2ec6 r5 z1 fs adjust rset 75 cvbs/b cvbs/g y/cvbs c/r analog power plane p p p p lpf lpf lpf to video connector ground (power supply connector) +5v (vcc) vaa schottky diodes schottky diodes rf modulator 75 trap rf modulator lpf 22 pf 1.8 m h 270 pf bt856/7 c9 + c1 l1 rf modulator rf 330 pf gnd to filter dac output 22 pf 1.8 m h 270 pf 330 pf audio 82 zin = 1 k (note 1) 75 (note 1) 75 75 (note 1) (note 2) location description vendor part number c1ec8 0.1 m f ceramic capacitor erie rpe112z5u104m50v c9 47 m f capacitor mallory csr13f476km l1 ferrite bead - surface mount fair-rite 2743021447 r1 1 k w 5% resistor rset 1% metal film resistor dale cmf-55c z1 1.235 v voltage reference lm385bze1.2, lm4041-1.2 trap ceramic resonator murata tpsx.xmj or mb2 (where x.x =sound carrier frequency in mhz) schottky diodes bat85 (bat54f dual) hp 5082-2305 (1n6263) siemens bat 64-04 (dual) the vendor numbers above are listed only as a guide. substitution of devices with similar characteristics will not affect the performance of the bt856/7.
brook t ree 35 pc b oard c onsiderations power and ground planes bt856/7 figure 16. typical connection diagram and parts list (internal voltage reference) notes: 1. values for 700 mv scart /peritv may be 20% higher when using rgb inputs. 2. some modulators may require ac coupling capacitors (10 m f). vaa comp vref_out vref_in gnd c7 c8 c2ec6 fs adjust rset cvbs/b cvbs/g y/cvbs c/r analog power plane p p p p lpf lpf lpf to video connector ground (power supply connector) +5v (vcc) vaa schottky diodes schottky diodes rf modulator 75 trap rf modulator lpf 22 pf 1.8 m h 270 pf bt856/7 c9 + c1 l1 rf modulator rf 330 pf gnd to filter dac output 22 pf 1.8 m h 270 pf 330 pf audio 82 zin = 1 k 75 (note 1) 75 (note 1) 75 75 (note 1) (note 2) location description vendor part number c1ec8 0.1 m f ceramic capacitor erie rpe112z5u104m50v c9 47 m f capacitor mallory csr13f476km l1 ferrite bead - surface mount fair-rite 2743021447 rset 1% metal film resistor dale cmf-55c trap ceramic resonator murata tpsx.xmj or mb2 (where x.x = sound carrier frequency in mhz) schottky diodes bat85 (bat54f dual) hp 5082-2305 (1n6263) siemens bat 64-04 (dual) the vendor numbers above are listed only as a guide. substitution of devices with similar characteristics will not affect the performance of the bt856/7.
brook t ree 36 pc b oard c onsiderations decoupling bt856/7 decoupling device decoupling for optimum performance, all capacitors should be located as close as possible to the device, and the shortest possible leads (consistent with reliable operation) should be used to reduce the lead inductance. chip capacitors are recommended for minimum lead inductance. radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. val- ues are chosen to have self-resonance above the pixel clock. power supply decoupling the best power supply performance is obtained with a 0.1 m f ceramic capacitor decoupling each group of vaa pins to gnd. the capacitors should be placed as close as possible to the device vaa and gnd pins and connected with short, wide traces. the 47 m f capacitor shown in figures 15 and 16 is for low-frequency power supply ripple; the 0.1 m f capacitors are for high-frequency power supply noise rejection. when a linear regulator is used, the power-up sequence must be verited to pre- vent latchup. a linear regulator is recommended to tlter the analog power supply if the power supply noise is greater than or equal to 200 mv. this is especially im- portant when a switching power supply is used, and the switching frequency is close to the raster scan frequency. about 5% of the power supply hum and ripple noise less than 1 mhz will couple onto the analog outputs. comp decoupling the comp pin must be decoupled to vaa pin 66, typically with a 0.1 m f ceramic capacitor. low-frequency supply noise will require a larger value. the comp ca- pacitor must be as close as possible to the comp and vaa pins. a surface-mount ceramic chip capacitor is preferred for minimal lead inductance. lead inductance degrades the noise rejection of the circuit. short, wide traces will also reduce lead inductance. vref _in decoupling a 0.1 m f ceramic capacitor should be used to decouple this input to gnd.
brook t ree 37 pc b oard c onsiderations signal interconnect bt856/7 signal interconnect digital signal interconnect the digital inputs to the bt856/7 should be isolated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power plane or analog output signals. most of the noise on the analog outputs will be caused by excessive edge rates (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. the digital edge rates should not be faster than necessary, as feedthrough noise is proportional to the digital edge rates. lower-speed applications will bene? from using lower-speed logic (3? ns edge rates) to reduce data-related noise on the an- alog outputs. transmission lines will mismatch if the lines do not match the source and des- tination impedance. this will degrade signal ?elity if the line length re?ction time is greater than one-fourth the signal edge time (refer to brooktree application notes an-11 and an-12). line termination or line-length reduction is the solu- tion. for example, logic edge rates of 2 ns require line lengths of less than 4 inches without use of termination. ringing may be reduced by damping the line with a se- ries resistor (30?00 w ). radiation of digital signals can also be picked up by the analog circuitry. this is prevented by reducing the digital edge rates (rise/fall time), minimizing ringing with damping resistors, and minimizing coupling through pc board capacitance by routing the digital signals at a 90 degree angle to any analog signals. the clock driver and all other digital devices must be adequately decoupled to prevent noise generated by the digital devices from coupling into the analog circuitry. analog signal interconnect the bt856/7 should be located as close as possible to the output connectors to min- imize noise pickup and re?ections caused by impedance mismatch. the analog outputs are susceptible to crosstalk from digital lines; digital traces must not be routed under or adjacent to the analog output traces. to maximize the high-frequency power supply rejection, the video output sig- nals should overlay the ground plane. for maximum performance, the analog video output impedance, cable imped- ance, and load impedance should be the same. the load resistor connection be- tween the video outputs and gnd should be as close as possible to the bt856/7 to minimize re?ections. unused analog outputs should be connected to gnd.
brook t ree 38 pc b oard c onsiderations applications information bt856/7 applications information esd and latchup considerations correct esd-sensitive handling procedures are required to prevent device damage. device damage can produce symptoms of catastrophic failure or erratic device be- havior with leaky inputs. all logic inputs should be held low until power to the device has settled to the speci?d tolerance. dac power decoupling networks with large time constants should be avoided; they could delay vaa power to the device. ferrite beads must be used only for analog power vaa decoupling. inductors cause a time constant delay that induces latchup. latchup can be prevented by ensuring that all vaa and gnd pins are at the same potential and that the vaa supply voltage is applied before the signal pin voltages. the correct power-up sequence ensures that any signal pin voltage will never exceed the power supply voltage. sync and burst timing table 9 lists the resolutions and clock rates for the various modes of operation. table 10 lists the horizontal counter values for the end of horizontal sync, start of color burst, end of color burst, and the ?st active pixel for the various modes of operation. the front porch is the interval before the next expected falling hsync* when outputs are automatically blanked. the horizontal sync width is measured between the 50% points of the falling and rising edges of horizontal sync. the start of color burst is measured between the 50% point of the falling edge of horizontal sync and the ?st 50% point of the color burst amplitude (nominally +20 ire for ntsc/pal? and 150 mv for pal?, d, g, h, i, n, n-argentina above the blanking level). the end of color burst is measured between the 50% point of the falling edge of horizontal sync and the last 50% point of the color burst envelope (nominally +20 ire for ntsc/pal? and 150 mv for pal?, d, g, h, i, n, n-argentina above the blanking level). table 9. field resolutions and clock rates for various modes of operation operating mode active resolution (pixels) total resolution (pixels) clkx1 frequency (mhz) ntsc/pal? ccir601 pal?, d, g, h, i, n, n?rgentina ccir601 ntsc square pixel (note 1) pal?, d, g, h, i, n, n?rgentina square pixel (note 1) 720 x 240 720 x 288 640 x 240 768 x 288 858 x 262 864 x 312 780 x 262 944 x 312 13.5000 13.5000 12.2727 14.7500 note 1: pal? and pal? (argentina) not available in square pixel format.
brook t ree 39 pc b oard c onsiderations applications information bt856/7 clock and subcarrier stability the color subcarrier is derived directly from the clkx2 input, hence any jitter or frequency deviation of clkx2 will be transferred directly to the color subcarrier. jitter within the valid clkx2 cycle interval (i.e., for correct registering of clkx1 and data) will result in hue noise on the color subcarrier on the order of 0.9?.6 de- grees per nanosecond. random hue noise can result in degradation in am/pm noise ratio (typically around 40 db for consumer media such as videodiscs and vcrs). periodic or coherent hue noise can result in differential phase error (which is limited to 10 degrees by fcc cable tv standards). any frequency deviation of the clock from nominal will challenge the subcarrier tracking capability of the destination receiver. this may range from a few parts-per-million (ppm) for broad- cast equipment to 100 ppm for industrial equipment to a few hundred ppm for con- sumer equipment. greater subcarrier tracking range generally results in poorer subcarrier decoding dynamic range, so that receivers that tolerate jitter and wide subcarrier frequency deviation will introduce more noise in the decoded image. crystal-based clock sources with maximum deviations of 100 ppm produce the best results for consumer and industrial applications, while temperature-compen- sated clock sources with tighter tolerances may be warranted for broadcast or more stringent pal (e.g., type i) applications. some applications call for maintaining correct subcarrier-horizontal phasing (sc-h) for correct color framing, which requires subcarrier coherence within speci?d tolerances over a four-?ld interval for 525-line systems or 8 ?lds for 625-line systems. any clkx2 interruption (even during vertical blanking inter- val) which results in mis-registration of the clkx1 input or non-standard pixel counts per line can result in sc-h excursions outside the ntsc limit of 40 de- grees (reference eia rs170a) or the pal limit of 20 degrees (reference ebu d23-1984). any deviation of the number clkx1 cycles between hsync* falling edges when in slave mode may result in automatic mode switching unless the internal control registers at 8-bit subaddress 0xdc are set for the desired mode of operation. table 10. horizontal counter values for various video timings horizontal counter value operating mode front porch (note 1) end of horizontal sync start of burst end of burst first active pixel clocks m s clocks m s clocks m s clocks m s clocks m s ntsc ccir601 paleb, d, g, h, i, n ccir601 ntsc square pixel paleb, d, g, h, i, n square pixel palem ccir601 (note 1, table 9) palen (argentina) ccir601 (note 1, table 9) 15 11 18 23 15 11 1.11 0.81 1.47 1.42 1.11 0.81 63 63 58 69 63 63 4.66 4.66 4.73 4.68 4.66 4.66 72 76 65 83 78 76 5.33 5.62 5.30 5.63 5.78 5.62 105 106 96 116 111 111 7.77 7.84 7.82 7.86 8.22 8.22 123 133 117 155 123 133 9.10 9.84 9.53 10.51 9.10 9.84 notes: 1. in slave mode, since front porch timing is triggered by the previous hsync pulse, any deviation from nominal line length will affect the front porch duration. 2. timings may differ from broadcast (e.g. fcc) or distribution (e.g. rs170) standards, in part due to detnitions. blank* may be asserted to prolong porch intervals. chroma blanking is effective 10 clock cycles later.
brook t ree 40 pc b oard c onsiderations applications information bt856/7 filtering rf modulator connection the bt856/7 internal upsampling ?ter alleviates external ?tering requirements by moving signi?ant sampling alias components above 19 mhz and reducing the sinx/x aperture loss up to the ?ters passband cutoff of 5.75 mhz. while typical chrominance subcarrier decoders can handle the bt856/7 output signals without analog ?tering, the higher frequency alias products pose some emi concerns and may create troublesome images when introduced to an rf modulator. when the video is presented to an rf modulator, it should be free of energy in the region of the aural subcarrier (4.5 mhz for ntsc, 5.5?.5 mhz for pal), hence some ad- ditional frequency traps may be necessary when the video signal contains funda- mental or harmonic energy (as from un?tered character generators) in that region. where better frequency response ?tness is required, some peaking in the analog ?ter is appropriate to compensate for residual digital ?ter losses with suf?ient margin to tolerate 10% reactive components. a three-pole elliptic ?ter (1 inductor, 3 capacitors) with a 6.75 mhz passband can provide at least 45 db attenuation (including sinx/x loss) of frequency compo- nents above 20 mhz and provide some ?xibility for mild peaking or special traps. an inductor value with a self-resonant frequency above 80 mhz is chosen so that its intrinsic capacitance contributes less than 10% of the total effective circuit val- ue. the inductor itself may induce 1% (0.1 db) loss. any additional ferrites intro- duced for emi control should have less than 5 w impedance below 5 mhz to minimize additional losses. the capacitor to ground at the bt856/7 output pin is compensated for the parasitic capacitance of the chip plus any protection diodes and lumped circuit traces (about 22 pf+5 pf/diode). some tlter peaking can be accomplished by splitting the 75 w source impedance across the reactive pi tlter network. however, this will also introduce some chrominance-luminance delay distortion in the range of 10e20 ns for a maximum of 0.5 db boost at the subcarrier frequency. the tlter network feeding an rf modulator may include the aforementioned trap, which could take two forms depending on the depth of attenuation and type of resonator device employed. the rf modulator typically has a high input imped- ance (about 1k 30%) and loose tolerance. consequently, the amplitude variation at the modulator input will be greater, especially when the trap is properly termi- nated at the modulator input for maximum effect. some modulators video or aural tdelity will degrade dramatically when overdriven, so the value of the effective termination (nominally 37.5 w ) may need to be adjusted downward to maintain suftcient linearity (or depth of modulation margin) in the rf signal. when using a two section strap (e.g., when stereo, sap, or am aural carriers are generated), some impedance isolation (e.g., buffer) may be required before the trap to obtain ?attest frequency response. see figures 15 and 16.
brook t ree 41 pc b oard c onsiderations i 2 c programming bt856/7 i 2 c programming data transfer on the i 2 c bus figure 17 shows the relationship between iic data and iic clock to be used when programming the i 2 c bus. if the bus is not being used, both iic data and iic clock lines must be left high. every byte put onto the iic data line should be 8 bits long (msb ?st), fol- lowed by an acknowledge bit, which is generated by the receiving device. each data transfer is initiated with a start condition and ended with a stop con- dition. the ?st byte after a start condition is always the address byte. if this is the devices own address, the device will generate an acknowledge by pulling the iic data line low during the ninth clock pulse, then accept the data in subsequent bytes (autoincrementing the subaddress) until another stop condition is detected. the eighth bit of the address byte is the read/write bit (high = read from ad- dressed device, low = write to the addressed device) so, for the bt856/7, the ad- dress is only considered valid if the r/w bit is low. data bytes are always acknowledged during the ninth clock pulse by the ad- dressed device. note that during the acknowledge period the transmitting device must leave the iic data line high. premature termination of the data transfer is allowed by generating a stop con- dition at any time. when this happens, the bt856/7 will remain in the state de?ed by the last complete data byte transmitted. any master acknowledge subsequent to reading the chip id (subaddress 0x89) is ignored. figure 17. iic diagram note 1: acknowledge generated by bt856/7. 1 iic clock 23456789 1 23456789 123456 789 subsequent bytes and acknowledge interpreted as data values for autoincremented subaddress locations iic data msb lsb (note 1) start condition stop condition subaddress (xx) data (xx) main address (xx) (note 1) (note 1)
brook t ree 43 p arametric i nformation dc electrical parameters table 11. recommended operating conditions parameter symbol min typ max units power supply vaa 4.75 5.00 5.25 v ambient operating temperature ta 0 70 c dac output load (note 1) rl 37.5 w nominal rset using internal vref using external vref (1.23 v) rset 71.5 73.2 w w external vref vref 1.15 1.235 1.32 v note 1: dc component not to exceed 80 w . table 12. absolute maximum ratings parameter symbol min typ max units vaa (measured to gnd) 7.0 v voltage on any signal pin (note 1) gnd ?.5 vaa + 0.5 v analog output short circuit duration to any power supply or common isc inde?ite ambient operating temperature ta ?5 +125 c storage temperature ts ?5 +150 c junction temperature tj +150 c vapor phase soldering (1 minute) tvsol 220 c stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the oper- ational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended peri- ods may affect device reliability. note 1: this device employs high-impedance cmos devices on all signal pins. it should be handled as an esd-sen- sitive device. voltage on any signal pin that exceeds the power supply or ground voltage by more than 0.5 v can cause destructive latchup.
brook t ree 44 p arametric i nformation dc characteristics bt856/7 dc characteristics table 13. dc characteristics parameter symbol min typ max units video d/a resolution output current-dac code 511 (iout fs) output voltage-dac code 511 video level error using external reference (rset trim, nominal load) using internal reference (nominal resis- tors output capacitance 99 34.08 1.28 22 9 40 5 5 bits ma v % % pf digital inputs (except those speci?d below) input high voltage input low voltage input high current (vin = 2.4 v) input low current (vin = 0.4 v) input capacitance (f = 1 mhz, vin = 2.4 v) vih vil iih iil cin 2.0 gnd ?.5 7 vaa + 0.5 0.8 1 ? v v m a m a pf iic clock, iic data sleep input input high voltage input low voltage clkx2 input input high voltage input low voltage vil vih vil vih vil gnd ?.5 2.0 gnd ?.5 2.4 gnd ?.5 1.0 vaa + 0.5 0.6 vaa + 0.5 0.8 v v v v v digital outputs output high voltage (ioh = ?00 m a) output low voltage (iol = 3.2 ma) three-state current output capacitance voh vol ioz cdout 2.4 10 0.4 50 v v m a pf vref_in input current iref_in 10 m a ?ecommended operating conditions, ntsc ccir 601 operation, and clkx1 frequency = 13.5 mhz. as the above parameters are guaranteed over the full temperature range, temperature coef?ients are not speci?d or required. typi- cal values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 v.
brook t ree 45 p arametric i nformation ac characteristics bt856/7 ac characteristics table 14. ac characteristics (1 of 2) parameter eia/tia 250c ref symbol min typ max units hue accuracy (note 1, note 3) color saturation accuracy (note 1, note 3) chroma am/pm noise (note 3) 1 mhz red field 1.5 1.5 ?2 2.5 2.0 % db rms differential gain (note 2) differential phase (note 2) snr (unweighted 100 ire y ramp tilt correct) (note 2) rms peak periodic 100 ire multiburst (note 3) chroma/luma gain ineq (note 3) chroma/luma delay ineq (note 3) short time distortion 100ire/pixel (note 3) luminance nonlinearity (note 2) chroma/luma intermod (note 2) chroma nonlinear gain (note 2) chroma nonlinear phase (note 2) 6.2.2.1 6.2.2.2 6.3.1 6.3.2 6.1.1 6.1.2.2 6.1.2 6.1.6 6.2.1 6.2.3 6.2.4.1 6.2.4.2 55 ? ?.0 ?.0 1.5 1.0 60 56 ?.2 ? 4 0 2 0.1 6 3 1.0 1.0 % p? p? db rms db p-p ire ire ns % % ire ire pixel/control setup time (note 4) pixel/control hold time (note 4) ycmode/gamma* setup time (note 5) ycmode/gamma* hold time (note 5) control output delay time (note 4) control output hold time (note 4) 1 2 1 2 3 4 7 3 6 4 2 17 ns ns ns ns ns ns clock frequency (i/t) clkx1 setup time clkx1 hold time clkx2 frequency clkx2 pulse width low time clkx2 pulse width high time fin 5 6 12.27 8 0 24.54 8 8 14.75 29.50 mhz ns ns mhz ns ns ?ecommended operating conditions, ntsc ccir 601 operation, and clkx1 frequency = 13.5 mhz. analog output load 75 pf. hsync*, vsync*, blank*, and field output load 75 pf. as the above parameters are guaranteed over the full temperature range, temperature coef?ients are not speci?d or required. typical values are based on nom- inal temperature, i.e., room temperature, and nominal voltage, i.e., 5 v. video input and output timing is shown in figures 18 and 19. notes: 1. 75/7.5/75/7.5 color bars normalized to burst. 2. guaranteed by characterization. 3. without post ?ter. guaranteed by design. 4. control pins are de?ed as: r0?7, g0?7, b0?7, blank*, hsync*, vsync*, field, ycmode, gamma*. 5. for ycmode and gamma* inputs in 8-bit yc mode only
brook t ree 46 p arametric i nformation ac characteristics bt856/7 pipeline delay input pixels to composite video input pixels to rgb output 25.5 10.5 25.5 10.5 25.5 10.5 t t vaa supply current 250 295 ma power-down mode current 15 ma ?ecommended operating conditions, ntsc ccir 601 operation, and clkx1 frequency = 13.5 mhz. analog output load 75 pf. hsync*, vsync*, blank*, and field output load 75 pf. as the above parameters are guaranteed over the full temperature range, temperature coef?ients are not speci?d or required. typical values are based on nom- inal temperature, i.e., room temperature, and nominal voltage, i.e., 5 v. video input and output timing is shown in figures 18 and 19. table 14. ac characteristics (2 of 2) parameter eia/tia 250c ref symbol min typ max units figure 18. 24-bit rgb and 16-bit ycrcb video input and output timing clkx2 clkx1 5 6 r[0:7],g[0:7] b[0:7],blank*, hsync*, vsync*, field, ycmode, hsync*, vsync* field (output) 1 2 3 4 pipeline cvbs/b, cvbs/g, y/cvbs, c/r gamma* 2.4 .8
brook t ree 47 p arametric i nformation ac characteristics bt856/7 figure 19. 8-bit ycrcb video input and output timing clkx2 clkx1 blank*, hsync*, vsync* g[0:7] or b[0:7] (ycbcr input) 1 2 3 4 cvbs/b, cvbs/g, y/cvbs, c/r 1 gamma* (input) 2 hsync*, vsync* field (output) 6 cx y ycmode 2 pipeline 5 5 6 2.4 .8 1
brook t ree 48 p arametric i nformation package drawing bt856/7 package drawing figure 20. 68-pin plcc
brook t ree 49 p arametric i nformation revision history bt856/7 revision history revision change from previous revision a initial release b revised pin assignments for rgb outputs c added pal?, pal? (argentina), final ac/dc speci?ations
brooktree corporation 9868 scranton road san diego, ca 92121-3707 (619) 452-7580 1(800) 2-bt-apps tlx: 383 596 fax: (619) 452-1249 l856001 rev. c brook t ree printed on recycled paper

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